One of the main objectives of a set top box chip is to extract, decode and display audio and video. In order to do so, the set top box chip has to find relevant transport packets in the incoming bitstream (i.e., carrying audio and video for the program of interest), extract the audio/video payloads and pass the payloads on to the audio/video decoder portion of the set top box chip. Parsing of the incoming transport stream is done by the transport demultiplexer in the set top box chip. Moving Picture Experts Group (MPEG-2) transport streams are made up of transport packets with different packet identification (PID) values in the packet headers that differentiate between distinct substreams of data.
To be able to find transport packets carrying audio and video of the program of interest, together with other program components like teletext or subtitles, the transport demultiplexer has to know under what PID values to expect the different program components. To build up that information, the incoming bitstream carries service information (SI). The service information is carried in transport packets with specific IDs and has to be parsed by the transport demultiplexer to transform from raw packet data to meaningful tables. The meaningful tables lead to other tables, audio and video information.
A major task of transport stream processing in a set top box is to extract service information from the raw, incoming transport packets without prior knowledge (i.e., starting from fixed IDs and then extending according to table contents and user choices). Conventionally, the extraction task is tackled in a two step approach. In the first step, conventional dedicated transport hardware reduces the overall amount of data by discarding all data currently not of interest. Only SI data that has passed the hardware filtering steps in the transport block (i.e., a substantially reduced amount of data) is posted to buffers in an off-chip memory.
For data posting, the transport makes use of a memory interface in the set top box chip. Whenever hardware has posted a meaningful portion of data to a cyclic buffer, the hardware interrupts a host central processing unit (CPU) that then performs the second stage of processing. The host CPU reads posted data from the off-chip memory, analyses the data further and typically builds relevant tables from the raw data. The contents of the table are then used to adjust transport register settings to get audio and video to the A/V decoder.
While the two stage approach is a compromise between host CPU loading and flexible processing, the two stage approach creates substantial duplication of processing steps. In existing solutions, the second step has to re-do substantial portions of the filtering to differentiate between more than one table under a single PID and checking. A substantial amount of status data from the first step is simply lost in the data posting.